The present invention relates to non-volatile memory devices, such as electrically or ultra-violet erasable and electrically programmable memory cells, and particularly to a method for increasing read current in non-volatile memory devices.
An electrically erasable and programmable read-only memory (EEPROM) cell or a UV erasable and electrically programmable read-only memory (EPROM) cell consists of a single transistor incorporating a floating gate (1T cell). For programmable logic applications, an EEPROM cell can include both an access transistor and a floating gate storage transistor. In general, EPROM cells and EEPROM cells will be referred to as non-volatile memory cells (or transistors). In many memory and programmable logic applications, both complementary-symmetry metal-oxide-semiconductor (CMOS) transistors and non-volatile memory cells are used.
Advances in technology demand increased performance in smaller packages. As a result, a trend has emerged towards scaling down components. Such scaling includes a reduction in power consumed by the components as well as a physical reduction in component size. Historically, the minimum feature sizes of transistors have been scaled down from 0.5 microns, to 0.35 microns to 0.25 microns to 0.18 microns. It is expected that this trend will continue to provide sub-0.18 micron transistors.
To scale down CMOS transistors, scaling is performed in both the vertical dimension and the horizontal dimensions. To scale down a CMOS transistor in the vertical dimension, the gate oxide thickness is reduced. Thus, for 0.5, 0.35, 0.25 and 0.18 micron processes, CMOS gate oxide thickness are 120, 70, 50, and 30 Angstroms, respectively. To scale down a CMOS transistor in the horizontal dimensions, both the length and width of the transistors must shrink proportionally. If the CMOS transistor channel length is reduced without reducing the gate oxide thickness, the CMOS transistor will exhibit punch through. Punch through occurs when the source depletion layer and the drain depletion layer touch each other. As the minimum feature size of transistors is scaled down, a reduction in the nominal operating voltage (i.e., the VCC supply voltage) is required. For example, for 0.5, 0.35, 0.25 and 0.18 micron technologies, the nominal VCC supply voltages have been 5 Volts, 3.3 Volts, 2.5 Volts and 1.8 Volts, respectively.
In CMOS transistors, power is proportional to both the VCC supply voltage and channel current. Because transistor speed directly depends on the channel current, most efforts for reducing power in devices utilizing CMOS transistors focus on power supply scaling. Scaling down the VCC power supply voltage causes the speed of a scaled down transistor to stay the same or increase, but proportionally reduces power consumption.
Non-volatile memory cells cannot be scaled down by the same factor as CMOS transistors. More specifically, the vertical dimensions of a non-volatile memory cell cannot be scaled down by the same factor, because the thickness of the tunneling oxide and the thickness of the insulation layer between the floating gate and the control gate must be maintained for purposes of data retention and endurance. Because the vertical dimensions of the non-volatile memory cell cannot be significantly reduced, the horizontal dimensions (i.e., the cell channel) cannot be significantly reduced.
The read channel current in a non-volatile memory transistor is defined as the current through the non-volatile memory transistor during a read operation. The read channel current in a non-volatile memory transistor is proportional to the square of the VCC supply voltage divided by the channel length. A reduction in the VCC supply voltage without a corresponding reduction in the channel length of the non-volatile memory transistor results in a lowered read channel current. The lower read channel current causes a significant degradation of the speed of a non-volatile memory transistor.
It would be desirable to increase the channel current in a non-volatile memory transistor that is operating at a reduced VCC voltage supply source without providing a corresponding reduction in transistor channel length.
Current methods for increasing the read channel current in non-volatile memory transistors include increasing the gate voltage, increasing the drain voltage, and increasing the coupling ratio of the non-volatile memory transistor.
The first method for increasing channel current during a read operation involves increasing the voltage applied to the gate of the non-volatile memory transistor. As described above, the cause of the lowered channel current is the lowered VCC voltage supply source. During a read operation, this VCC voltage supply source may be pumped to a larger voltage, thereby increasing the voltage applied to the gate of the non-volatile memory transistor. However, the use of a charge pump requires additional delay required to pump up the gate voltage and also requires additional space on the integrated circuit for the charge pump circuitry.
The second method for increasing channel current during a read operation involves increasing the voltage applied to the drain of the non-volatile memory transistor. The channel current is proportional to the electrical field between the source and the drain. Therefore, increasing the drain voltage causes the electrical field to increase, thereby increasing the channel current. However, the increased voltage on the drain causes an increase in read disturb of the non-volatile memory transistor. Read disturb occurs when read conditions cause hot electron injection from the channel region into the floating gate, thereby disturbing the contents of the non-volatile memory transistor. This read disturb typically limits the maximum drain voltage applied to the non-volatile memory transistor during a read operation to less than 2.0 Volts.
The third method of increasing the channel current during a read operation is to increase the coupling ratio between the control gate and the floating gate of the non-volatile memory transistor. The voltage of the floating gate controls the channel current during a read operation. This voltage on the floating gate is a function of the coupling ratio of the non-volatile memory transistor. The coupling ratio is proportional to the relative areas of the control gate and the floating gate. The coupling ratio is the percentage of the voltage applied to the control gate (i.e. the VCC voltage supply source) that is transmitted to the floating gate. However, to increase the coupling ratio of a non-volatile memory transistor, the cell size of the non-volatile memory transistor has to increase, thereby requiring more space on the integrated circuit.
As described above, current methods for increasing read channel current in non-volatile memory transistors operating at a lowered voltage require a larger cell size or increase the possibility of read disturb. It would be desirable to increase the read channel current in a non-volatile memory transistor without more space on the integrated circuit or increasing the possibility of read disturb.
Accordingly, the present invention describes a method to increase the speed of a non-volatile memory transistor by increasing the read channel current in the non-volatile memory transistor. This increase in speed is accomplished without increasing the VCC voltage supply source or decreasing the channel length of the non-volatile memory transistor.
The increase in read channel current is accomplished by applying a low voltage to the substrate region of the non-volatile memory transistor, while grounding the source of the non-volatile memory transistor. If the non-volatile memory transistor is located in an array, the low voltage is applied to the source and drain of non-volatile memory transistors on unselected bit lines to inhibit junction leakage current from these unselected non-volatile memory transistors.
The design can be simplified by applying zero Volts to the source and drain of non-volatile memory transistors on unselected bit lines. However, this will result in higher substrate leakage.
The present invention will be more fully understood in view of the following description and drawings.